A power switch, and a method, for use with a power switch having a field-effect transistor (FET) including source, drain and gate terminals. The power switch includes a first field-effect transistor (FET) having a first drain coupled to the drain terminal, a first source coupled to the source terminal, and a first gate; and, a second FET having a second drain coupled to the drain terminal, a second source coupled to the source terminal, and a second gate. The second FET has a gate length (L.sub.G) that is greater than or less than an L.sub.G of the first FET and has a length of a drain (L.sub.D) that is greater than or less than an L.sub.D of the first FET. The power switch further includes a control circuit coupled to the gate terminal, the first gate, and the second gate.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation application of and claims priority under 35 U.S.C. .sctn.120 to commonly-owned, U.S. application Ser. No. 10/796,405, filed Mar. 8, 2004, now U.S. Pat. No. 6,937,086 which is a continuation-in-part U.S. application Ser. No. 10/327,586, filed on Dec. 20, 2002, now U.S. Pat. No. 6,703,888, which is a continuation of U.S. application Ser. No. 10/172,484, filed on Jun. 13, 2002, now U.S. Pat. No. 6,529,056, which is a continuation of U.S. application Ser. No. 09/853,356, filed on May 11, 2001, now U.S. Pat. No. 6,433,614, which is a continuation of U.S. application Ser. No. 09/798,008, filed on Mar. 2, 2001, now abandoned, the entire contents of which are hereby incorporated by reference.
