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Synchronising circuit
 
   
Document Number
US Patent 7236556
Issued Date
June 26, 2007
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Inventors
Joy; Andrew (Northampton,GB)
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Abstract
In an integrated circuit receiving multiple serial data streams in parallel, a local clock is generated from each data stream and is synchronized with the data stream. Sometimes a data stream may have no transitions making it difficult to keep the clock synchronized with its data. A clock channel is provided, which always has edges. A circuit is provided for each data stream which measures the time elapsed since the data stream had an edge. After a certain period, the phase of the local clock is nudged towards that of the clock channel. Thereafter, the longer there are no edges on the data stream the more frequently nudges towards the phase of the clock channel are made.
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Number of Claims:
39
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Owner
Published
June 26, 2007
Application Number
10/624,280
Filed
July 22, 2003
US Classification
375/371   375/376
Int'l Classification
H04L   25/00   (20060101)   H03D   3/24   (20060101)  
Examiner
Priority Data
Jul 22, 2002 [EP] 02255105
USPTO Field of Search
375/371   375/376   375/375   375/354   375/327   375/294   327/147   327/156   329/325   329/360   342/103  
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