A multiple-core processor providing a flexible cache directory scheme. In one embodiment, a processor may include a second-level cache including a number of cache banks and a respective number of cache directories corresponding to the cache banks. The processor may further include a number of processor cores configured to access the cache banks, as well as core/bank mapping logic coupled to the second-level cache and the processor cores. Each of the processor cores may include a respective first-level cache. Each of the respective cache directories may be configured to store directory state information associated with portions of respective first-level caches of at least two of the processor cores. If fewer than all of the cache banks are enabled, the core/bank mapping logic may be configured to completely map directory state information associated with each respective first-level cache of enabled processor cores to respective cache directories associated with enabled cache banks.
PRIORITY CLAIM
This application claims benefit of priority of U.S. Provisional Patent Application No. 60/584,064, entitled "Yield Recovery Technique for Integrated Circuits" and filed on Jun. 30, 2004.
Provided is a system to communicate data in a computing environment, comprising an interleaving mechanism operable to interleave data being communicated across the computing environment according to a selected interleaving protocol; and an interleaving instruction set operable on the interleaving mechanism providing operating instructions to the interleaving mechanism in accordance with the selected interleaving protocol wherein the data can be interleaved between one or more data channels of the computing environment and within one or more data channels of the computing environment.
A method for recovering lost cache capacity in a multi core chip having at least one defective core including identifying the cores contained in the chip that are viable cores and identifying at least one core contained in the chip that is defective. The method also includes identifying the cache memory local to the defective core and determining a redistribution of the cache resources local to the at least one defective core among the viable cores. The method also features dividing the cache memory local to the at least one defective core according to the redistribution determination and determining the address information associated with the cache memory local to the at least one defective core. The method also features providing the address information associated with the cache memory associated with the defective core to at least one of the viable cores, facilitating the supplementation of the cache memory local to the viable cores with the cache memory associated with the defective core.
A method for analyzing a set of spawning pairs, where each spawning pair identifies at least one speculative thread. The analysis may be practiced via software in a compiler, binary optimizer, standalone modeler, or the like. The analysis may include determining a predicted execution time for a sequence of program instructions, given the set of spawning pairs, for a target processor having a known number of thread units, where the target processor supports speculative multithreading. The method is further to select a spawning pair, according to a greedy approach, if the spawning pair provides a performance enhancement, in terms of decreased execution time due to increased parallelism, when the speculative thread is spawned during execution of a code sequence. Other embodiments are also described and claimed.
