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Mirror suppression circuit and receiver using such circuit
   
Document Number
US Patent 7242730
Issued Date
July 10, 2007
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Abstract
A mirror suppression circuit includes a first quadrature signal path coupled between quadrature signal input and output terminals and an error correction circuit for correction of amplitude and phase errors in a carrier modulated quadrature signal. To obtain a suppression of both amplitude and phase imbalance of the carrier modulated quadrature signal as well as signal amplitude variations, a quadrature output of the error correction circuit is coupled to an error detection circuit. The error detection circuit detects amplitude and phase errors and provides amplitude and phase control signals to the error correction circuit for a negative feed back of the amplitude and phase errors. The amplitude and phase control signals vary with products of components of the quadrature signal and components of a quadrature reference signal.
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Number of Claims:
20
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Published
July 10, 2007
Application Number
10/509,210
Filed
May 1, 2003
US Classification
375/346  
Int'l Classification
H03D   1/04   (20060101)  
Examiner
Assistant Examiner
Attorney/Law Firm
Priority Data
May 07, 2002 [EP] 02076835
USPTO Field of Search
375/346  
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