A memory capable of performing a refresh operation without increasing current consumption is provided. This memory comprises a plurality of memory cells storing data, a delay circuit outputting a first address signal corresponding to the memory cells received from outside for a normal access operation with a delay of a prescribed period, a refresh control circuit outputting a second address signal corresponding to any of the memory cells subjected to a refresh operation of the data and a switching circuit switching and outputting the first address signal output from the delay circuit and the second address signal output from the refresh control circuit.
A memory includes an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation, a refresh division control portion dividing the refresh operation into a read operation and a rewrite operation and an address determination portion determining whether or not an address to be subjected to the refresh operation and an address to be subjected to the external access operation during the refresh operation coincide with each other.
