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Apparatus employing predictive failure analysis based on in-circuit FET on-resistance characteristics
   
Document Number
US Patent 7248979
Issued Date
July 24, 2007
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Abstract
A computing system includes a semiconductor which sources/sinks current to/from components within the system, an in-circuit semiconductor on-resistance characterization circuit which measures the on-resistance of the semiconductor, and a processor which periodically or continuously engages the characterization circuit over the life of the semiconductor to obtain a series of on-resistance measurements. Depending on the type of semiconductor used, or depending on arbitrary design limitations, the computing system predicts semiconductor failure based on either a relative mode or an absolute mode. The relative mode is useful when using FET's since on-resistance values vary significantly. In the relative mode, an optional NVRAM is used to store one or more on-resistance measurements which may serve as a reference for assuring proper circuit operation within tolerable deviations from the reference. In the absolute mode, one or more optional thresholds are utilized to assure that circuit operation remains in a known good region.
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Number of Claims:
17
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Published
July 24, 2007
Application Number
11/124,940
Filed
May 9, 2005
US Classification
702/65  
Int'l Classification
G01R   27/00   (20060101)  
Examiner
USPTO Field of Search
702/57   702/64   702/65  
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