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Semiconductor memory device with reduced package test time
 
   
Document Number
US Patent 7249294
Issued Date
July 24, 2007
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Abstract
A semiconductor memory device capable of performing a package test with bandwidth other than the default bandwidth without any wiring modification with respect to package option pads reduces package test time. The present invention implements the other package options based upon the wire bonding with an internal option. According to the operation mode, buffer control signals are used to control a VDD or VSS applied to the package option pads via the wire bonding. Buffer control signal are generated using a mode register reset. The buffer receiving the buffer control signal outputs the signal corresponding to the wiring state of the package option pad, blocks the signal path from the package option pads, and outputs a signal corresponding to a package option other than the default package option.
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Number of Claims:
23
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Owner
Hynix Semiconductor Inc. (Ichon-shi, Kyoungki-do,KR)
Published
July 24, 2007
Application Number
10/331,728
Filed
December 31, 2002
US Classification
714/718   365/201
Int'l Classification
G11C   29/00   (20060101)   G11C   7/00   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Jun 24, 2002 [KR] 2002-35451 Jun 24, 2002 [KR] 2002-35457
USPTO Field of Search
714/718  
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