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Reliable BEOL integration process with direct CMP of porous SiCOH dielectric
 
   
Document Number
US Patent 7253105
Issued Date
August 7, 2007
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Abstract
The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.
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Number of Claims:
20
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Published
August 7, 2007
Application Number
11/063,152
Filed
February 22, 2005
US Classification
438/674   257/E21.206 257/E21.576 257/E21.589
Int'l Classification
H01L   21/44   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
438/622   438/631   438/674  
Related Patents
7485566 - Method of manufacturing semiconductor device - Owned by NEC Electronics Corporation (Kawasaki, Kanagawa,JP)

A method of manufacturing a semiconductor device is provided. The method includes: (A) forming an insulating film with a porous structure on a substrate; (B) forming a trench in the insulating film, the trench being used for forming an interconnection; (C) depositing a metal layer over the insulating film such that the trench is filled in with the metal layer; (D) forming the interconnection by removing an excess metal layer outside the trench; (E) modifying a surface of the insulating film to form a modified layer on the insulating film; and (F) forming a metal film selectively on the interconnection by using plating solution after the (E) modifying process.

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