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Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells
   
Document Number
US Patent 7256415
Issued Date
August 14, 2007
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Abstract
Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially "U" shaped. The double memory cells comprise two essentially "U" shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the "U" shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.
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Number of Claims:
10
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Published
August 14, 2007
Application Number
11/140,780
Filed
May 31, 2005
US Classification
257/2   257/4 257/E45.003 438/104 438/900
Int'l Classification
H01L   47/00   (20060101)  
Examiner
USPTO Field of Search
257/2  
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