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SEU and SEFI fault tolerant computer
   
Document Number
US Patent 7260742
Issued Date
August 21, 2007
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Abstract
A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run additional processors. Additionally, a hardened SEFI circuit is provided to periodically send a signal to the process which, in the case of a processor not in the SEFI state, initiates production by the processor of a "correct" response. If the correct response is not received within a particular time window, the SEFI circuit initiates progressively severe actions until a reset is achieved.
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Number of Claims:
16
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Owner
Published
August 21, 2007
Application Number
10/767,477
Filed
January 28, 2004
US Classification
714/21   714/17 714/822
Int'l Classification
G06F   11/00   (20060101)  
Examiner
Assistant Examiner
Parent Case
CROSS REFERENCE TO RELATED APPLICATIONS This patent application claims priority of provision patent application 60/442,727, filed Jan. 28, 2003.
USPTO Field of Search
714/16   714/17   714/21  
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