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Minimizing resist poisoning in the manufacture of semiconductor devices
   
Document Number
US Patent 7262129
Issued Date
August 28, 2007
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Abstract
The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).
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Number of Claims:
8
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Owner
Published
August 28, 2007
Application Number
10/993,791
Filed
November 19, 2004
US Classification
438/638   257/E21.027 257/E21.577 257/E21.579 438/637 438/672
Int'l Classification
H01L   21/4763   (20060101)  
Examiner
USPTO Field of Search
438/637   438/638   438/672  
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