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Gate layouts for transistors
   
Document Number
US Patent 7265041
Issued Date
September 4, 2007
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Abstract
A transistor and a method of fabricating the transistor are provided. The transistor includes a semiconductor material comprising drain regions and source regions formed in alternating rows or columns. The transistor also includes polysilicon chains overlaying the top of the semiconductor material, disconnected from and substantially parallel to one another, and separating the drain regions from the source regions. The method includes providing a semiconductor material, growing a first insulating layer on top of the semiconductor material, depositing a polysilicon layer on top of the first insulating layer, defining a plurality of chains in the polysilicon layer, the plurality of chains being disconnected from and substantially parallel to one another, and forming a plurality of drain regions and a plurality of source regions in the semiconductor material in alternating rows or columns. The plurality of chains separates the plurality of drain regions from the plurality of source regions.
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Number of Claims:
12
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Owner
Micrel, Inc. (San Jose, CA)
Published
September 4, 2007
Application Number
11/311,995
Filed
December 19, 2005
US Classification
438/587   438/128 438/197
Int'l Classification
H01L   29/74   (20060101)   H01L   27/082   (20060101)   H01L   27/102   (20060101)   H01L   29/70   (20060101)   H01L   31/11   (20060101)   H01L   31/111   (20060101)  
Examiner
Attorney/Law Firm
USPTO Field of Search
438/128   438/129   438/128   438/129   438/128   438/129  
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