or
Bookmark and Share
Method and apparatus for implementing subthreshold leakage reduction in LSDL
   
Document Number
US Patent 7268590
Issued Date
September 11, 2007
Link
Map
Abstract
A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
15
Comments:
no comments yet
Published
September 11, 2007
Application Number
11/304,142
Filed
December 15, 2005
US Classification
326/95   326/97 326/98
Int'l Classification
H03K   19/096   (20060101)  
Examiner
Attorney/Law Firm
USPTO Field of Search
326/95   326/96   326/97   326/98  
Related Patents
Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us