An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherein each of the first operations depend on at least one of the second operations during use. A first number of the first operations is less than or equal to a maximum. It is ambiguous, for a first received operation in the first virtual channel, whether the first received operation is one of the first operations or the second operations. A total number of the first plurality of buffers exceeds the maximum.
CROSS REFERENCE TO RELATED APPLICATION
This application is a divisional application of and claims priority to U.S. Patent Application having an application Ser. No. 10/434,921; filed May 9, 2003, now U.S. Pat. No. 7,114,403; which application claims priority to U.S. Provisional Patent Application Ser. No. 60/380,740, filed May 15, 2002; and in which both applications are hereby incorporated by reference in this application.
