A storage controlling apparatus comprises a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and is to be written to a cache memory or a memory. The storage controlling apparatus further comprises a data storing unit which receives the store data from the store port, temporarily stores the store data, and comprised between the store port and the cache memory or the memory, and a data write controlling unit which controls a write of the store data from the store port to the data storing unit.
Data are stored on a random-access storage medium. A user set of data is received. The user set of data is mapped to multiple frames. For each frame, error-correction bytes are generated over the data mapped to that frame. In addition, the data mapped to that frame are written to a number of data blocks of that frame and the error-correction bytes generated for that frame are written to a number of error-correction blocks of that frame. At least one of the number of error-correction blocks and the number of data blocks differs among at least some of the frames.
