Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell. The inputs of the additional multiplexer connect to the data input and data output of the boundary cell.
This Application claims benefit to Provisional Application 60/049,960, filed Jun. 17, 1997; Provisional Application 60/049,863, filed Jun. 17, 1997; Provisional Application 60/047,954, filed Jun. 17, 1997; Provisional Application 60/047,961, filed May 29, 1997; Provisional Application 60/047,956, filed May 29, 1997; Provisional Application 60/047,951, filed May 29, 1997; Provisional Application 60/047,947, filed May 29, 1997; Provisional Application 60/047,886, filed May 29, 1997; Provisional Application 60/047,883, filed May 29, 1997; and Provisional Application 60/028,821, filed Oct. 18, 1996.
This application is a divisional of application Ser. No. 10/225,662, filed Aug. 22, 2002, now U.S. Pat. No. 6,594,789, issued Jul. 15, 2003; which is a divisional of Ser. No. 09/864,502, filed May 24, 2001, now U.S. Pat. No. 6,442,721 issued on Aug. 27, 2002; which is a divisional of application Ser. No. 08/931,791, filed Sep. 16, 1997, now U.S. Pat. No. 6,260,165, issued Jul. 10, 2001.
Generating a near-minimal test pattern set for overlapping residue circuit trees in a residue network includes resolving a residue function of residue circuits through the network and making note of any gate at which the residue function thereof does not produce the assigned vector output for a given assigned set of input vectors. Where such gates cannot be resolved during one set of vector assignments, the test set that is complete up to the offending gate may be saved, and resolution of the residue function may be started from another node in the network. Multiple test sets may be generated, the combined application of which will exhaustively test each gate in the network.
Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.
