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Semiconductor integrated circuit
   
Document Number
US Patent 7282957
Issued Date
October 16, 2007
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Abstract
In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H level. In this case, when none of a plurality of pieces of data is selected using a selection signal, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor of the second dynamic circuit is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.
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Number of Claims:
45
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Published
October 16, 2007
Application Number
11/188,740
Filed
July 26, 2005
US Classification
326/96   326/112
Int'l Classification
H03K   19/096   (20060101)   H03K   19/20   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Jul 27, 2004 [JP] 2004-218244
USPTO Field of Search
326/95   326/96   326/97   326/98   326/112  
Related Patents
7541841 - Semiconductor integrated circuit - Owned by Panasonic Corporation (Osaka,JP)

In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0 to D2 is selected using selection signals S0 to S2, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor Tr6 of the second dynamic circuit 1B is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected. This circuit is used in a predetermined circuit, such as, for example, a forwarding path of a data path, a crossbar bus switch, or an input portion of a reconfigurable processing unit.

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Description
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