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Enhanced JTAG interface
   
Document Number
US Patent 7284174
Issued Date
October 16, 2007
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Abstract
An enhanced JTAG interface provides an additional clock output at any desired I/O port of a logic device during normal operation. The interface includes a boundary scan data cell associated with each I/O port that enables either input data to the I/O port in a normal mode or routes the boundary scan input data during a JTAG operation. A control cell is associated with each data cell for selectively enabling either a normal mode or a JTAG mode of the boundary scan cell. A set of JTAG instructions enable/disable JTAG operation and select JTAG functions. The boundary scan data cell is modified to incorporate a multiplexing arrangement to selectively route the JTAG clock to the I/O port when required. The control cell is modified to selectively enable/disable the routing of the JTAG clock in the boundary scan data cell.
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Number of Claims:
13
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Owner
STMicroelectronics Pvt Ltd. (Uttar Pradesh,IN)
Published
October 16, 2007
Application Number
11/024,574
Filed
December 29, 2004
US Classification
714/727   714/729
Int'l Classification
G01R   31/317   (20060101)   G01R   31/316   (20060101)  
Examiner
Assistant Examiner
Priority Data
Dec 30, 2003 [IN] 1644/DEL/2003
USPTO Field of Search
714/727   714/726   714/742   714/25   714/45   714/724  
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