Method embodiments including providing control information to a memory device is provided. The control information includes a first code which specifies that a write operation be initiated in the memory device. A signal is provided that indicates when the memory device is to begin sampling write data that is stored in the memory core during the write operation. A first bit of the write data is provided to the memory device during an even phase of a clock signal. A second bit of the write data is provided to the memory device during an odd phase of the clock signal.
This application is a continuation of U.S. patent application Ser. No. 10/094,547 filed on Mar. 8, 2002 now U.S. Pat. No. 6,931,467; which is a continuation of U.S. patent application Ser. No. 09/870,322 filed on May 29, 2001 (now U.S. Pat. No. 6,470,405); which is a continuation of U.S. patent application Ser. No. 09/561,868 filed on May 1, 2000 (now U.S. Pat. No. 6,591,353); which is a continuation of U.S. patent application Ser. No. 09/480,767 filed on Jan. 10, 2000 now U.S. Pat. No. 6,810,449; which is a continuation of U.S. patent application Ser. No. 08/979,402 filed on Nov. 26, 1997 (now U.S. Pat. No. 6,122,688); which is a divisional of U.S. patent application Ser. No. 08/545,292 filed on Oct. 19, 1995 (now U.S. Pat. No. 5,748,914).
