or
Bookmark and Share
Methods and apparatus for maintaining cache coherency
 
   
Document Number
US Patent 7287126
Issued Date
October 23, 2007
Link
Inventors
Map
Abstract
Methods and apparatus for maintaining cache coherency and reducing write-back traffic by using an enhanced MESI cache coherency protocol are disclosed. The enhanced MESI protocol includes the traditional MESI cache states (i.e., modified, exclusive, shared, invalid, and pending) as well as two additional cache states (i.e., enhanced modified and enhanced exclusive). An enhanced modified cache line is a cache line that is different than main memory and a copy of the cache line may be in another cache. An enhanced exclusive cache line is a cache line that is not modified and a copy of the cache line is in another cache in a modified state. Depending on the state of a victimized cache line, an internal inquiry may be issued to other caches and/or a write-back operation may be performed prior to victimizing the selected cache line.
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
26
Comments:
no comments yet
Owner
Intel Corporation (Santa Clara, CA)
Published
October 23, 2007
Application Number
10/630,164
Filed
July 30, 2003
US Classification
711/145  
Int'l Classification
G06F   12/00   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
711/144   711/145  
Related Patents
Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us