A method for testing signals of integrated circuits (ICs). According to the invention, a first IC chip successively drives a number of test patterns one at a time. At the receiving end, a second IC chip latches in the test patterns one by one. Meanwhile, the second IC chip determines whether a currently latched test pattern is correct or not. If it is incorrect and at least an error bit occurs, depending on the type of the test patterns, the second IC chip indicates that there exists ground bounce or power bounce in a signal trace corresponding to the error bit.
A method of generating digital test patterns for testing a number of wiring interconnects is described. A first set of test patterns is generated; the number of test patterns in the first set is related to said number of wiring interconnects, and defines a first set of code words. From the first set of code words, a second set of code words is selected. The number of code words in the second set is equal to said number of wiring interconnects, and the selection of the second set of code words is such that the sum of the transition counts for the code words in the second set is minimized.
A method, apparatus, and system are disclosed for tuning core voltages of processors. One embodiment is a method for software execution. The method includes varying core voltages of plural processors operating in lockstep to determine an operating range for each of the plural processors, and adjusting the core voltages of the plural processors within the operating range to tune the plural processors.
A method for noise suppression for a system implementation of an integrated circuit design is described. First clock operating parameters for logic blocks of the integrated circuit design are obtained. Second clock operating parameters for input/output banks of the integrated circuit design are obtained. At least one switching frequency associated with at least one power supply source is obtained. First and second capacitor values for the at least one power supply source are determined responsive to the first clock operating parameters, the second clock operating parameters, and the at least one switching frequency. The first capacitor values are associated with a first frequency range of operation and the second capacitor values are associated with a second frequency range of operation which is higher than the first frequency range of operation. Third capacitor values for suppression of anti-resonances are determined.
An integrated software tool for system noise management is described. A system noise management suite for an assembly includes an integrated circuit design to be coupled to a circuit board design. The system includes three modules and a user interface. The first module is configured to determine at least one type of bounce voltage for the assembly. The second module is configured to identify decoupling capacitances for the assembly to reduce power distribution system noise. The third module is configured to estimate jitter caused by the integrated circuit design. The user interface is coupled to the first module, the second module, and the third module for input of information for the first module, the second module, and the third module.
A method for estimating jitter of an integrated circuit design is described. A description of logic blocks of the integrated circuit design is obtained. A description of input/output blocks of the integrated circuit design is obtained. A first type of a first jitter induced by operation of a logic block onto one or more first clock signals external to the logic block is determined. A second type of a second jitter induced by operation of an input/output block on one or more second clock signals external to the input/output block is determined.
