An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.
RELATED APPLICATION
This application is a continuation of Application Ser. No. 11/348,359, filed Feb. 7, 2006, now U.S. Pat. No. 7,154,776, which is a divisional of Application Ser. No. 10/328,032, filed Dec. 26, 2002, now U.S. Pat. No. 7,020,008, which claims priority of Japanese Application No. 2002-288755, filed Oct. 1, 2002. Application Ser. No. 10/328,032, filed Dec. 26, 2002 is also a Continuation-In-Part of U.S. patent application Ser. No. 10/166,784, filed Jun. 12, 2002 which claims priority of Japanese Application No. 2001-394285, filed Dec. 26, 2001, the contents of which are hereby incorporated by reference.
Priority Data
Dec 26, 2001 [JP] 2001-394285 Oct 01, 2002 [JP] 2002-288755
