Nanotube on gate FET structures and applications of such, including n.sup.2 crossbars requiring only 2n control lines. A non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and a channel region of a second semiconductor type of material disposed between the source and drain region. A gate structure is made of at least one of semiconductive or conductive material and is disposed over an insulator over the channel region. A control gate is made of at least one of semiconductive or conductive material. An electromechanically-deflectable nanotube switching element is in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure. The network is such that the nanotube switching element is deflectable into contact with the other of the gate structure and the control gate structure in response to signals being applied to the control gate and one of the source region and drain region. Certain embodiments of the device have an area of about 4 F.sup.2. Other embodiments include a release line is positioned in spaced relation to the nanotube switching element, and having a horizontal orientation that is parallel to the orientation of the source and drain diffusions. Other embodiments provide an n.sup.2 crossbar array having n.sup.2 non-volatile transistor devices, but require only 2n control lines.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority under 35 U.S.C. .sctn. 119(e) to U.S. Provisional Pat. Apl. Ser. No. 60/459,224, filed on Mar. 28, 2003, entitled Nanotube-On-Gate FET Structures and Applications, which is incorporated herein by reference in its entirety.
This application is related to the following U.S. applications, the contents of which are incorporated herein in their entirety by reference: U.S. Provisional Apl. Ser. No. 60/459,223 filed on Mar. 28, 2003, entitled NRAM Bit Selectable Two-Device Nanotube Array; and U.S. patent application Ser. No. 10/810,962, filed on the same day as the present application, entitled NRAM Bit Selectable Two-Device Nanotube Array. U.S. Provisional Patent Application No. 60/459,253, filed on Mar. 28, 2003, entitled Single Transistor with Integrated Nanotube (NT-FET), and U.S. patent application Ser. No. 10/459,253, filed on the same day as the present application, entitled A Four Terminal Non-Volatile Transistor Device. U.S. Provisional Patent Application Ser. No. 60/459,222, filed on Mar. 28, 2003, entitled Non-Volatile RAM Cell and Array using Nanotube Switch Position for Information State, and U.S. patent application Ser. No. 10/810,936, filed on the same day as the present application, entitled Non-Volatile Ram Cell and Array Using Nanotube Switch Position for Information State.
