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Document Number
US Patent 7294932
Issued Date
November 13, 2007
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Abstract
The semiconductor device 100 includes a multilayer wiring structure formed on the semiconductor substrate. The multilayer wiring structure includes at least a first inter layer dielectric film 120 in which interconnects 124 are formed, and at least a second inter layer dielectric film 122 in which vias 126 are formed. The multilayer wiring structure includes a circuit region 110 in which the interconnects 124 and the vias 126 are formed, a seal ring region 112 formed around the circuit region 110 and in which seal rings surrounding the circuit region 110 in order to seal the circuit region 110 are formed, and a peripheral region 114 formed around the seal ring region 112. The semiconductor device 100 further includes dummy vias 136 formed of a metal material, formed in the second interlayer dielectric film 122 at the peripheral region 114.
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Number of Claims:
14
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Published
November 13, 2007
Application Number
11/183,820
Filed
July 19, 2005
US Classification
257/758   257/409 257/759 257/E23.145
Int'l Classification
H01L   23/48   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Jul 28, 2004 [JP] 2004-220073
USPTO Field of Search
257/758  
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