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Receiver having a variable threshold slicer stage and a method of updating the threshold levels of the slicer stage
   
Document Number
US Patent 7295630
Issued Date
November 13, 2007
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Abstract
A receiver having a variable bit slicer for detecting bits in a demodulated signal, comprises a demodulator (14) for deriving a demodulated bit rate signal, means (36) for storing a plurality of threshold values, each of the threshold values being selectively adjustable, means (28, 38) for selecting the threshold value for comparison with the current bit signal (S.sub.n) in response to a sequence of N bits (where N is at least 2) (B.sub.n-1, B.sub.n-2) received prior to the current bit (B.sub.n) and means (38, 40) for using the current bit to update the selected threshold value.Also disclosed is a method of dc offset correction.
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Number of Claims:
8
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Owner
NXP B.V. (Eindhoven,NL)
Published
November 13, 2007
Application Number
10/015,848
Filed
December 10, 2001
US Classification
375/316   375/346 375/348
Int'l Classification
H03K   9/00   (20060101)   H03D   1/04   (20060101)  
Examiner
Assistant Examiner
Priority Data
Jan 04, 2001 [GB] 0100202.1
USPTO Field of Search
375/316   375/346   375/348   375/350  
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