An approach is provided for efficiently decoding low density parity check (LDPC) codes. An LDPC decoder includes a memory for storing a mapped matrix that satisfies a plurality of parallel decodable conditions for permitting a lumped memory structure. Additionally, the decoder includes a parallel processors accessing edge values from the stored mapped matrix decode the LDPC codes. The above approach has particular applicability to satellite broadcast systems.
RELATED APPLICATIONS
This application is related to, and claims the benefit of the earlier filing date under 35 U.S.C. .sctn. 119 (e) of, U.S. Provisional Patent Application (Ser. No. 60/484,974) filed Jul. 3, 2003, entitled "General Parallel Decodable LDPC Codes"; the entirety of which is incorporated herein by reference.
