A memory cell array is formed by providing a plurality of memory cells along a substrate, where each of the memory cells includes a storage element and an access transistor. A plurality of bit lines are formed that extend along a first direction of the substrate. A plurality of active area lines and a plurality of isolation trenches are also formed in the semiconductor substrate, with the isolation trenches being adjacent the active area lines such that each isolation trench is disposed between and electrically isolates a first active area line from a second active area line. The access transistors are at least partially formed in the active area lines and electrically couple corresponding storage elements to corresponding bit lines via bit line contacts, and at least a portion of each bit line contact is located at an intersection of a bit line and a corresponding active area line.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. patent application Ser. No. 11/004,881, filed Dec. 7, 2004, now U.S. Pat. No. 7,139,184 and titled "Memory Cell Array," the entire contents of which are hereby incorporated by reference.
