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Copper plating of semiconductor devices using single intermediate low power immersion step
   
Document Number
US Patent 7312149
Issued Date
December 25, 2007
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Abstract
A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.
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Number of Claims:
21
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Published
December 25, 2007
Application Number
10/840,095
Filed
May 6, 2004
US Classification
438/674   257/E21.175 257/E21.586 438/678 438/687
Int'l Classification
H01L   21/44   (20060101)  
Examiner
Attorney/Law Firm
USPTO Field of Search
438/674   438/678   438/687  
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