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Method and apparatus for synchronization of shared memory in a multiprocessor system
   
Document Number
US Patent 7313794
Issued Date
December 25, 2007
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Abstract
Method and apparatus for synchronizing access to a memory shared among a plurality of processors is described. In one example, each of the plurality of processors includes a primary bus for communicating with the memory and a secondary bus. A synchronization block is coupled to the secondary bus of each of the plurality of processors. The synchronization block includes at least one semaphore for controlling access among the plurality of processors to at least one data segment stored within the memory.
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Number of Claims:
27
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Owner
Xilinx, Inc. (San Jose, CA)
Published
December 25, 2007
Application Number
10/354,813
Filed
January 30, 2003
US Classification
718/102   710/108
Int'l Classification
G06F   9/46   (20060101)   G06F   13/00   (20060101)  
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USPTO Field of Search
718/104   718/102   710/241   710/108  
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