The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation of application Ser. No. 10/726,492 filed Dec. 4, 2003 now U.S. Pat. No. 6,839,814, which is divisional of application Ser. No. 09/750,094 filed Dec. 29, 2000, now U.S. Pat. No. 6,675,266, and a divisional of application Ser. No. 10/435,386 filed May 12, 2003, now U.S. Pat. No. 6,775,746, which is also a divisional of application Ser. No. 09/750,094, filed Dec. 29, 2000 now U.S. Pat. No. 6,675,266; this application is also a continuation of application Ser. No. 10/743,069 filed Dec. 23, 2003 now U.S. Pat. No. 6,904,502, which is a continuation of application Ser. No. 10/435,386 filed May 12, 2003 now U.S. Pat. No. 6,775,746, which is a divisional of application Ser. No. 09/750,094 filed Dec. 29, 2000 now U.S. Pat. No. 6,675,266, all of which are hereby incorporated herein in their entireties by reference thereto.
