A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the IC at respective local clock regions. A master clock generator generates a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions.
This application is a Divisional of U.S. application Ser. No. 10/125,591 filed on Apr. 19, 2002 now U.S. Pat. No. 6,943,610 which incorporated herein by reference.
