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System and method for analyzing electrical failure data
   
Document Number
US Patent 7319935
Issued Date
January 15, 2008
Link
Map
Abstract
A system and method to perform analysis on test results of multiple integrated circuits. Based on the analysis, the system and method display a wafer map having map indicators representing statistical values of the test results.
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Number of Claims:
66
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Owner
Published
January 15, 2008
Application Number
10/365,997
Filed
February 12, 2003
US Classification
702/59   356/237.4
Int'l Classification
G01R   31/00   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
702/57   702/58   702/59   702/68   702/81   702/57   702/58   702/59   702/150   702/179   702/62   702/80   702/90   702/122   702/168   702/57   702/58   702/59   702/188   700/58   700/83   700/95   438/10   438/14   438/17   714/25   714/37   365/201   382/141   356/237.1   356/237.2   356/237.4  
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