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Automatic extension of clock gating technique to fine-grained power gating
 
   
Document Number
US Patent 7323909
Issued Date
January 29, 2008
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Abstract
A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.
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Number of Claims:
20
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Owner
Sequence Design, Inc. (Santa Clara, CA)
Published
January 29, 2008
Application Number
11/193,149
Filed
July 29, 2005
US Classification
326/93   326/95 326/96
Int'l Classification
H03K   19/00   (20060101)  
Examiner
USPTO Field of Search
326/93   326/94   326/95   326/96   326/97   326/98  
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