Memory testing at system startup, such as boot POST, of an information handling system is accelerated by adjusting memory testing routines to use instructions that take advantage of optimizations made to information handling system and CPU architectures. For instance, memory test iterations in one Mbyte portions using 128-bit SIMD registers, 64-bit MMX registers, ADD and SUB instructions, the MOVNTDQ instruction, and relying on an initial setting of the gate A20 and protected mode result in a substantially accelerated memory test.
