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Method and apparatus for implementing assertions in hardware
 
   
Document Number
US Patent 7328374
Issued Date
February 5, 2008
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Abstract
A method, apparatus, and computer instructions in a processor for checking assertions. A determination by the processor is made as to whether metadata for an assertion is associated with the memory location, in response to detecting a change in data in a memory location. The data to the assertion is compared by the processor, in response to the metadata being associated with the memory location. An error is generated by the processor if the assertion is invalid, with respect to the data. The processor checks the assertions for validity.
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Number of Claims:
30
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Published
February 5, 2008
Application Number
10/835,485
Filed
April 29, 2004
US Classification
714/42  
Int'l Classification
G06F   11/00   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
714/42  
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