An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at which the circuit device is tested. Thus, the tester can generate stimulus vectors for multiple sweep points without requiring control system intervention. Pass/fail indicators, each of which represents pass/fail results associated with a sweep point, are derived from the test results and stored in a Fail Capture Memory. A pass/fail boundary of the DUT can be determined from the contents of the Fail Capture Memory.
RELATED APPLICATIONS
The present application is a continuation of U.S. patent application Ser. No. 10/247,188, filed on Sep. 19, 2002, now U.S. Pat. No. 6,975,956, the contents of which are hereby incorporated by reference in its entirety.
