A memory cell having a bit line contact is provided. The memory cell may be a 6F.sup.2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.
CROSS REFERENCE TO RELATED APPLICATIONS
The present application is a division of U.S. patent application Ser. No. 10/612,333, filed Jul. 2, 2003.
This application, which is itself identified below for clarity, is also a member of the following family of related U.S. patent applications: 09/653,638, filed Aug. 31, 2000, now U.S. Pat. No. 6,380,576; 10/056,183, filed Jan. 24, 2002, now U.S. Pat. No. 6,660,584; 10/209,504, filed Jul. 31, 2002, now U.S. Pat. No. 6,649,962; 10/612,333, filed Jul. 2, 2003; 10/649,507, filed Aug. 26, 2003, now U.S. Pat. No. 6,861,691; 10/933,201, filed Sep. 2, 2004 now U.S. Pat. No. 7,118,960; 10/986,246, filed Nov. 10, 2004, now U.S. Pat. No. 6,974,990; 11/041,689, filed Jan. 24, 2005; 11/041,357, filed Jan. 24, 2005 and 11/461,195 filed Jul. 31, 2006.
