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Method and circuit for controlling a PWM power stage
   
Document Number
US Patent 7332943
Issued Date
February 19, 2008
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Abstract
A method for controlling a PWM power stage is based upon dampening current peaks generated by switching of the PWM power stage. The PWM power stage includes at least two MOS transistors of opposite conductivity coupled between an output node of the PWM power stage and respective positive and negative supply lines, and respective free-wheeling diodes. The method includes forming the at least two MOS transistors such that their reverse conduction threshold voltage is smaller than a sum between their forward conduction threshold voltage and a forward voltage on the respective free-wheeling diode at which a pre-established current flows therethrough. The at least two MOS transistors are in a high impedance state by biasing respective control nodes at a turn-off voltage such that their gate-source voltage is between the forward conduction threshold voltage and a null voltage.
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Number of Claims:
16
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Owner
STMicroElectronics S.r.l. (Agrate Brianza,IT)
Published
February 19, 2008
Application Number
11/534,803
Filed
September 25, 2006
US Classification
327/112  
Int'l Classification
H03B   1/00   (20060101)  
Examiner
Priority Data
Sep 23, 2005 [IT] VA2005A0054
USPTO Field of Search
327/112   323/283   323/284  
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