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Memory device
 
   
Document Number
US Patent 7335907
Issued Date
February 26, 2008
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Abstract
A phase change memory device is provided which is constituted by memory cells using memory elements and select transistors and having high heat resistance to be capable of an operation at 140 degrees or higher. As a device configuration, a recording layer of which, of Zn--Ge--Te, content of Zn, Cd or the like is 20 atom percent or more, content of at least one element selected from the group consisting of Ge and Sb is less than 40 atom percent, and content of Te is 40 atom percent or more is used. It is thereby possible to implement the memory device usable for an application which may be performed at a high temperature such as an in-vehicle use.
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Number of Claims:
8
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Owner
Hitachi, Ltd. (Tokyo,JP)
Published
February 26, 2008
Application Number
10/790,881
Filed
March 3, 2004
US Classification
257/2   257/42 257/529 257/E27.004 257/E45.002 365/148 365/46
Int'l Classification
H01L   47/00   (20060101)  
Examiner
Priority Data
Mar 25, 2003 [JP] 2003-081724
USPTO Field of Search
257/2  
Related Patents
7502252 - Nonvolatile semiconductor memory device and phase change memory device - Owned by Elpida Memory Inc. (Tokyo,JP)

For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.

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Description
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