A bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a secondary RAID controller's bus bridge, which writes the data to its mirroring write cache. However, before writing the data, the second bus bridge automatically invalidates the cache buffers to which the data is to be written, which alleviates the primary controller's CPU from sending a message to the secondary controller's CPU to instruct it to invalidate the cache buffers. The secondary controller CPU programs its bus bridge at boot time with the base address of its mirrored write cache to enable it to detect that the cache buffer needs invalidating in response to the broadcast write, and with the base address of its directory that includes the cache buffer valid bits.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation-in-part (CIP) of the following co-pending Non-Provisional U.S. Patent Applications, which are hereby incorporated by reference in their entirety for all purposes:
TABLE-US-00001 Ser. No. Filing (Docket No.) Date Title 10/368,688 Feb. 18, BROADCAST BRIDGE APPARATUS FOR (CHAP.0101) 2003 TRANSFERRING DATA TO REDUNDANT MEMORY SUBSYSTEMS IN A STORAGE CONTROLLER 10/946341 Sep. 21, APPARATUS AND METHOD FOR (CHAP.0113) 2004 ADOPTING AN ORPHAN I/O PORT IN A REDUNDANT STORAGE CONTROLLER 11/178727 Jul. 11, METHOD FOR EFFICIENT INTER- (CHAP.0125) 2005 PROCESSOR COMMUNICATION IN AN ACTIVE-ACTIVE RAID SYSTEM USING PCI-EXPRESS LINKS
Pending U.S. patent application Ser. No. 10/946341 (CHAP.0113) is a continuation-in-part (CIP) of the following U.S. patent, which is hereby incorporated by reference in its entirety for all purposes:
TABLE-US-00002 U.S. Pat. No. Issue Date Title 6,839,788 Jan. 4, 2005 BUS ZONING IN A CHANNEL INDEPENDENT CONTROLLER ARCHITECTURE
Pending U.S. patent application Ser. No. 10/946341 (CHAP.0113) is a continuation-in-part (CIP) of the following co-pending Non-Provisional U.S. patent applications, which are hereby incorporated by reference in their entirety for all purposes:
TABLE-US-00003 Ser. No. Filing (Docket No.) Date Title 09/967,126 Sep. 28, CONTROLLER DATA SHARING USING A (4430-29) 2001 MODULAR DMA ARCHITECTURE 09/967,194 Sep. 28, MODULAR ARCHITECTURE FOR (4430-32) 2001 NETWORK STORAGE CONTROLLER 10/368,688 Feb. 18, BROADCAST BRIDGE APPARATUS FOR (CHAP.0101) 2003 TRANSFERRING DATA TO REDUNDANT MEMORY SUBSYSTEMS IN A STORAGE CONTROLLER
Pending U.S. patent application Ser. No. 10/946341 (CHAP.01 13) claims the benefit of the following expired U.S. Provisional Application, which is hereby incorporated by reference in its entirety for all purposes:
TABLE-US-00004 Ser. No. (Docket No.) Filing Date Title 60/554052 Mar. 17, 2004 LIBERTY APPLICATION BLADE (CHAP.0111)
Pending U.S. patent application Ser. No. 11/178,727 (CHAP.0125) claims the benefit of the following pending U.S. Provisional Application, which is hereby incorporated by reference in its entirety for all purposes:
TABLE-US-00005 Ser. No. (Docket No.) Filing Date Title 60/645,340 Jan. 20, 2005 METHOD FOR EFFICIENT INTER- (CHAP.0125) PROCESSOR COMMUNICATION IN AN ACTIVE-ACTIVE RAID SYSTEM USING PCI-EXPRESS LINKS
To be able to transmit a response packet to a target, which is the original request source node, even if, after issuing a request from a node to another, a bus ID/a device ID is replaced in the PCI-Express switch before said another node makes a response to the request source node in a PCI-Express communication system, which uses a PCI-Express switch. For that purpose, a unique node ID for indicating each node is set to the nodes, a channel ID is set to each channel used for data transfer, and the node ID of the transfer destination module, the channel ID of a channel used for the data transfer, and the packet type indicating that the packet is a request or a response are set in an address field of a packet of data transfer. For the data transfer, only a memory write request packet routed by address routing is used.
According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.
