A cascode circuit in which two field effect transistors ("FET") are connected in cascode has a first FET having its source grounded, a second FET having its source connected to the drain of the first FET, and a Schottky barrier diode having an anode connected to the source of the first FET and a cathode connected to the gate of the second FET.
An H.F. power amplifier is disclosed having a plurality of branches (10, 11, 12) switched in parallel. Each branch comprises a plurality of amplifier elements (T1, T4) switched in series. Resistors (R2, R5) enable the voltage (U_DS) applied to the amplifier elements (T1, T4) to be set at a fraction of a supply voltage (Ud) applied to the branches (10, 11, 12). Capacitors (C2, C4) are used to adjust the source impedance of the amplifier elements (T2, T4). In order to prevent the gate-drain voltage (U_GD) from exceeding the breakdown voltage of an amplifier element (T1, T4) and damaging the amplifier element (T1, T4), a limiting path (7) is connected according to the invention between the gate terminal (G) and the drain terminal (D) of the amplifier element (T1, T4), the limiting path (7) being switchable between a conducting state and a blocking state depending on the gate-drain voltage (U_GD).
An electron turbulence damping circuit (40) for a complimentary-symmetry unit (10') includes a first output device (12') having a first conductivity and a second output device (14') having a second conductivity that is opposite the conductivity of the first output device (12'). A common load connector (28') is secured in electrical communication between a load (30'), a first current output (18') of the first output device (12') and a second current output (24') of the second output device (14'). First and second resistive elements (42, 46) are secured in parallel between current inputs (16', 22') of the output devices (12', 14') and the common load connector (28'). The first and second resistive elements have a virtually identical resistance value that is greater than ten times a minimum impedance of the load (30'). The output devices (12', 14') may be transistors.