A liquid crystal display device includes a pair of substrates with a liquid crystal layer therebetween, a plurality of scanning signal lines and a plurality of video signal lines formed on one of said pair of substrates, a plurality of first electrodes on the one of said pair of substrates and a plurality of second electrodes on the one of said pair of substrates to drive the liquid crystal by a voltage difference with respect to the first electrode. The first electrodes have a bent form, and the second electrodes have a rectangular form.
CROSS REFERENCE TO RELATED APPLICATION
This is a continuation of U.S. application Ser. No. 10/400,448, filed Mar. 28, 2003, now U.S. Pat. No. 7,158,202, which is a continuation of U.S. application Ser. No. 10/237,756, filed Sep. 10, 2002, now U.S. Pat. No. 7,046,324, which is a continuation of U.S. application Ser. No. 09/841,100, filed Apr. 25, 2001, now U.S. Pat. No. 6,545,658, which is a continuation U.S. application Ser. No. 08/722,849, filed Sep. 26, 1996, now U.S. Pat. No. 6,266,116, the subject matter of which is incorporated by reference herein. This application is also related to U.S. application Ser. No. 10/637,495, filed Aug. 11, 2003, now U.S. Pat. No. 7,046,325, which is also a continuation of U.S. application Ser. No. 10/400,448.
Priority Data
Oct 04, 1995 [JP] 7-257366 Oct 09, 1995 [JP] 7-261235 Mar 27, 1996 [JP] 8-71787
An active matrix type liquid-crystal display device of IPS mode has its aperture ratio enhanced, thereby to realize an image display which has a wide angle of vision and which is clear and bright. A pixel portion (in FIG. 2) in the liquid-crystal display device comprises a TFT (115) which includes a semiconductor film formed over a substrate, and gate electrodes formed on a first insulating layer, a gate wiring line (104) which is formed on the first insulating layer, a common wiring line (113) which crosses the gate wiring line (104) through a second insulating layer, a pixel electrode (112) which is formed on the second insulating layer and which is connected with the TFT (115) of the pixel portion, a signal wiring line (106) which is formed so as to underlie the common wiring line (113) through the second insulating layer, and a connecting electrode (111) which is formed on the second insulating layer. The pixel electrode (112) and the common wiring line (113) are arranged so as to generate an electric field parallel to the plane of the substrate, and the signal wiring line (106) and the semiconductor film are connected through the connecting electrode (111).
