An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
CROSS-REFERENCE TO RELATED APPLICATIONS.
This application is a divisional and claims the priority benefit of U.S. patent application Ser. No. 11/041,687 filed Jan. 20, 2005 (now U.S. Pat. No. 7,227,383) and entitled "Low Leakage and Data Retention Circuitry," which claims the priority benefit of U.S. provisional patent application number 60/546,574 filed Feb. 19, 2004 and entitled "Power Management and Power Savings in Integrated Circuits" as well as the priority benefit of U.S. provisional patent application No. 60/586,565 filed Jul. 9, 2004 and entitled "Systems and Methods for I/O Power Island Management and Leakage Control on Integrated Circuits." The disclosure of each of the aforementioned applications is incorporated herein by reference.
An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
