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Buffered memory module and method for testing same
   
Document Number
US Patent 7350120
Issued Date
March 25, 2008
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Abstract
A buffered memory module includes a buffer circuit mounted and a plurality of memory devices mounted on the first surface of the board, the memory devices being electrically connected to the buffer circuit. The memory module also includes a plurality of test pads located on a second surface of the board and electrically connected to the buffer circuit.
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Number of Claims:
12
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Owner
Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do,KR)
Published
March 25, 2008
Application Number
10/833,322
Filed
April 28, 2004
US Classification
714/718   324/754 324/763
Int'l Classification
G11C   29/00   (20060101)   G01R   31/02   (20060101)  
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Priority Data
Jun 24, 2003 [KR] 10-2003-0041261
USPTO Field of Search
714/718  
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