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Cache error handling in a multithreaded/multi-core processor
   
Document Number
US Patent 7353445
Issued Date
April 1, 2008
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Abstract
In one embodiment, a processor comprises a cache shared by a plurality of threads in execution by the processor, an error detection unit coupled to the cache, and a fetch control unit. The error detection unit is configured to detect an error in data output by the cache responsive to an access corresponding to a first thread of a plurality of threads. Coupled to receive an indication of the error, the fetch control unit is configured to inhibit fetching for the first thread responsive to the error until the thread is redirected in response to the error and until the error is eliminated from the cache that includes the data.
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Number of Claims:
29
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Owner
Sun Microsystems, Inc. (Santa Clara, CA)
Published
April 1, 2008
Application Number
11/009,244
Filed
December 10, 2004
US Classification
714/758   711/125 711/126 711/138
Int'l Classification
H03M   13/00   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
711/138   711/126   711/125  
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