A data processor having: an instruction fetch unit for acquiring an instruction; and an instruction execution unit for execution, by pipeline processing, the instruction acquired by the instruction fetch unit. In the data processor, the instruction execution unit includes an execution pipeline pipelined into two or more stages for execution of the execution instruction, and an execution pipeline control unit capable of changing a stage to arrange an operation by the execution unit in according to the number of wait cycles until data required for execution of the execution instruction is fixed. The stage, where an operation by the execution unit is arranged, is changed according to the number of wait cycles until the data is fixed, whereby the number of input-fixing wait cycles increased by pipelining cache access can be reduced.
