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Imaging apparatus with delay and processor to weight lines of delayed image data
   
Document Number
US Patent 7358992
Issued Date
April 15, 2008
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Abstract
An imaging apparatus for performing efficient signal processing depending on the operational mode. In the finder mode, a CCD interface 21a decimates horizontal components of image data supplied from an image generating unit 10 to one-third and moreover processes the decimated image data with data conversion and resolution conversion to produce Y, Cb and Cr image data which are routed to and written in an image memory 32 over a memory controller 22. In the recording mode, the CCD interface 21a causes the image data from the image generating unit 10 to be written in the image memory 32 via memory controller 22 after decimation and gamma correction etc. The camera DSP 21c reads out the image data via memory controller 22 from the image memory 32 to effect data conversion for writing the resulting data via memory controller 22 in the image memory 32.
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Number of Claims:
6
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Owner
Sony Corporation (Tokyo,JP)
Published
April 15, 2008
Application Number
10/668,904
Filed
September 23, 2003
US Classification
348/231.99   348/311 348/E5.047
Int'l Classification
H04N   5/76   (20060101)  
Examiner
Parent Case
This is a divisional of U.S. patent application Ser. No. 09/354,476, filed Jul. 15, 1999 now U.S. Pat. No. 6,674,464.
Priority Data
Jul 17, 1998 [JP] 10-204089 Nov 25, 1998 [JP] 10-333965
USPTO Field of Search
348/311   348/316   348/317   348/231.99  
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