A circuit for providing power factor correction in accordance with an embodiment of the present application may include a boost converter circuit and a control circuit receiving as inputs a rectified AC input voltage from a rectifier, a signal proportional to current through the boost inductor and the DC bus voltage across the capacitor of the boost converter. The control circuit provides a pulse width modulated signal to control the on time of a PFC switch. The control circuit further includes a voltage regulator and a current regulator. The current regulator includes a difference device operable to subtract a signal proportional to the inductor current from the current reference signal, a PI controller adapted to receive the output of the difference device and provide a first control signal, a feed forward device operable to receive the rectified AC input voltage and to provide a second control signal with a smaller dynamic range than the AC input voltage, and an adder operable to add the first control signal to the second control signal to provide a PWM reference signal for generating the pulse width modulated signal. A zero crossing detector and vector rotator may be provided to provide a clean sinusoidal reference to the current regulator. A partial PFC regulator may be provide to provide partial mode PFC if desired.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims benefit of a priority to Provisional Application Ser. No. 60/675,541 filed Apr. 28, 2005 entitled DIGITAL IMPLEMENTATION OF PFC, the entire contents of which are hereby incorporated by reference herein.
This application is also related to U.S. patent application Ser. No. 11/267,516 entitled DIGITAL CONTROL OF BRIDGELESS POWER FACTOR CORRECTION CIRCUIT filed Nov. 4, 2005 which claims benefit of and priority to U.S. Provisional Application Ser. No. 60/626,117 filed Nov. 8, 2004 entitled DIGITAL CONTROL OF BRIDGELESS POWER FACTOR CORRECTION CIRCUIT, the entire contents of which are hereby incorporated by reference herein.
