The present invention provides a simultaneous switching (SS) test mode. SS test modules supporting an SS test mode are provided. When SS test mode is enabled, SS test mode data is driven on a data bus during an idle bus period. Otherwise, when SS test mode is disabled, no SS test mode data is driven on a data bus during an idle bus period.
In a debugging circuit and a controlling method of the debugging circuit, a mode judgment signal is generated which indicates that a central processing unit (CPU) is preparing to debug a predetermined program. Responsive to the mode judgment signal, a monitoring signal is generated indicative of an attempt by the CPU to execute the predetermined program during the debugging preparation. Furthermore, a transfer of an instruction code corresponding to the predetermined program is controlled so that the CPU is prevented from executing the predetermined program during the debugging preparation, responsive to the monitoring signal. Alternatively, in the debugging circuit and the method, instead of controlling the transfer of the instruction code responsive to the monitoring signal, another instruction code may be transferred to the CPU, responsive to the mode judgment signal. The another instruction code prevents the CPU from executing the predetermined program during the debugging preparation.
