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Description  |
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FIELD OF THE INVENTION
The present invention generally relates to programmable integrated circuit devices, and more particularly to a programmable matrix array with programmable connections made with phase-change materials.
BACKGROUND OF THE INVENTION
Generally, phase-change materials are capable of being electrically programmed between a first structural state where the material is generally amorphous and a second structural state where the material is generally crystalline. The term
"amorphous", as used herein, refers to a structural condition which is relatively less ordered or more disordered than a single crystal. The term "crystalline", as used herein, refers to a structural condition which is relatively more ordered than
amorphous. The phase-change material exhibits different electrical characteristics depending upon its state. For instance, in its crystalline, more ordered state the material exhibits a lower electrical resistivity than in its amorphous, less ordered
state. Each material phase can be conventionally associated with a corresponding logic value. For example, the lower resistance crystalline state may be associated with a logic "1" while the higher resistance amorphous state may be associated with a
logic "0".
Materials that may be used as a phase-change material include alloys of the elements from group VI of the Periodic Table. These group VI elements are referred to as the chalcogen elements and include the elements Te and Se. Alloys that include
one or more of the chalcogen elements are referred to as chalcogenide alloys. An example of a chalcogenide alloy is the alloy Ge.sub.2Sb.sub.2Te.sub.5 (also referred to as GST225).
A volume of phase-change material can be reversibly programmed between a high resistance state referred to as a reset state and a low resistance state referred to as a set state to provide a binary mode of operation. A volume of phase-change
material may also be programmed back and forth among three or more resistance states of intermediate resistance values to provide a multi-state mode of operation.
The phase-change materials may change states through application of an electrical signal. The electrical signal may be a voltage across or a current through the phase change material. The electrical signal may be in the form of one or more
electrical pulses. For example, the volume of material may be programmed from its high resistance reset state to its low resistance set state through application of an electrical pulse (e.g. a current pulse) referred to as a set pulse. While not
wishing to be bound by theory, it is believed that the set pulse is sufficient to change at least a portion of the volume of memory material from a less-ordered amorphous state to a more-ordered crystalline state. The volume of material may be
programmed back from the low resistance set state to the high resistance reset state by application of an electrical pulse (e.g. a current pulse) referred to as a reset pulse. While not wishing to be bound by theory, it is believed that application of a
reset pulse to the volume of material is sufficient to change at least a portion of the volume of memory material from a more-ordered crystalline state to a less-ordered amorphous state. It is conceivable that other forms of energy, such as optical
energy, acoustical energy or thermal energy, may be used to change the state of the volume of material.
A phase-material material may be used to form a phase-change memory. Typically, a phase-change memory is arranged as an array of phase-change cells having rows and columns with associated word lines and bit lines, respectively. Each memory cell
consists of a memory element which may be connected in series to an access device (also referred to as an isolation device). Examples of access devices include diodes, transistors and chalcogenide-based threshold switches. For use to connect logic it
is possible that such access devices may be connected to the lines to be coupled (for example at the end of the lines). Each memory cell is coupled between the respective word line (also referred to as a row line or an X line) and the respective bit
line (also referred to as a column line or a Y line).
The memory cells can be selected for a reading operation, for example, by applying suitable voltages to the respective word lines and suitable current or voltage pulses to the respective bit lines. A voltage reached at the bit line depends on
the resistance of the storage element (which corresponds to logic value stored in the selected memory cell).
For general memory use, either commodity or embedded, the logic value stored in the memory cell may be evaluated by sense amplifiers of the memory. Typically, a sense amplifier includes a comparator receiving the bit line voltage (or a related
voltage) and a suitable reference voltage. As an example, if the bit line driven by a read current achieves a voltage that is higher than the reference voltage for having higher resistance than the lower resistance case, the bit may be decreed to
correspond to a stored logic value "0", whereas if the bit line voltage is smaller than the reference voltage for the cell having lower resistance, then the bit may be decreed to correspond to the stored logic value "1".
Products, such as programmable logic devices, achieve random logic designs by providing standard logic interconnected to user specifications through an X-Y grid. This X-Y grid is conceptually similar to the X-Y grid of a memory array and
consists of X lines (corresponding, for example, to row or word lines) and a plurality of Y lines (corresponding, for example, to column or bit lines). The X lines typically cross (either over or under) the Y lines. The point at which an X line crosses
(either over or under) a Y line may be referred to as a cross-over point or a cross-point.
Preferably, the X lines are oriented in a first direction while the Y lines are oriented in a second direction different from the first direction. The X lines may be substantially perpendicular to the Y lines. The X lines are typically
physically spaced apart from the Y lines. The X lines are preferably insulated from the Y lines, however, it is possible that the X lines be connected to the Y lines such as through a shorting contact. When interconnecting logic instead of memory
elements of a memory array, the X-Y grid may be more random in spacing and irregular in length than the X-Y grid of the memory array.
In a memory array, the impedance between the X lines and the Y lines is preferably very high, like an open circuit, until the select device (also referred to as an isolation device) is enabled, such as by row selection. Such selection may entail
lowering or raising the X line. The isolation devices may be configured such that selecting a particular X line may lower the impedance between a memory element and a corresponding Y line, or between a memory element and a fixed voltage such as ground.
In contrast, the X-Y grid of conducting lines used for interconnecting logic (such as in a programmable logic array) may have a relatively linear resistance between the lines (instead of a piecewise linear resistance which may exist in a memory
array). That is, for a logic device such as a programmable logic array, an OPEN connection between an X line and a Y line may be represented by a resistance which is relatively high where an actual open circuit is intended. Likewise, a CLOSED
connection between an X line and a Y line may be represented by a resistance which is relatively low where an actual short circuit is intended.
The appropriate programmable connections between the X lines and Y lines at the cross-points may be programmed in different ways. One type of programming technology used to selectively determine connections is mask programming. This is done by
the semiconductor manufacturer during the chip fabrication process. Examples of mask programmable devices include mask programmable gate arrays, mask programmable logic arrays and mask programmable ROMs. In the case of mask programming, a CLOSED
connection may be an actual short circuit between an X line and a Y line at a cross-point while an OPEN connection may be an actual open circuit. This approach is characterized by good layout efficiency and performance, but higher tooling costs and time
delay to first article product since custom masks and layout are used for each different customer product.
In contrast to mask programmable devices, field programmable devices are programmed after they are manufactured. Examples of field programmable devices include programmable ROM (PROM), electrically erasable ROM (EEPROM), field programmable logic
arrays (FPLA), the programmable array logic device (PAL.RTM.), the complex programmable logic device (CPLD), and the field-programmable gate array (FPGA).
Field programmable devices make use of programmable connections at the cross-points of the X lines and the Y lines that can be programmed after the time of manufacture, and such programming may be done by the manufacturer to customer
specification, or by the OEM upon receipt, or by the end customer in the field, and even updated periodically such as through an internet download. Such programmable connections may also be referred to as cross-point switches.
For field programmable devices such as field programmable logic arrays, the programmable connections may be made so that a relatively high resistance between the lines represents an OPEN connection between the lines while a relatively low
resistance represents a CLOSED connection between the lines. Products with lower resistance for CLOSED connections may be faster with improved voltage margin, especially if the capacitance of the programmable connection tied to the interconnect lines is
low. Programmable connections having a higher resistance for OPEN connections may have lower leakage and better voltage margin (those connections intended to be OPEN connections may have a larger voltage difference across the lines).
The power drained off by the cross-points intended to be OPEN is a larger problem in larger logic arrays with more X-Y interconnects, and hence more cross-points. Hence, for non-mask programmed field programmable devices, whether tying together
logic or other electronic functions, there is a need for a programmable connection that can provide a relatively low resistance in CLOSED connections and a relatively high resistance in OPEN connections. Preferably, the programmable connection shall
also add little capacitance to the interconnected conductive lines and change the wafer fabrication process as little as possible.
A programmable connection for a field programmable device (such as a field programmable logic array-FPLA) may be a volatile or non-volatile connection (the difference being whether the device needs to be re-programmed each time power is
restored). For example, when a computer is turned off, the logic pattern desired in the field programmable logic chips may be stored in hard disc. Upon power-on restart, the logic interconnect pattern may be reloaded into the logic gates, at the
expense of delayed restart. Such a volatile approach, may store the state of the programmable connection at each cross-point node on a static RAM (SRAM) driving an n-channel cross point transistor, as shown in FIG. 1.
FIG. 1 shows an example of a programmable connection that uses an SRAM to drive the gate of an n-channel transistor at the cross-point of an X line X1 and a Y line Y1. The p-channel pull-up transistors T2 and T4, provide a high logic level near
the power supply, and the n-channel pull-down transistors T6 and T8, provide a pull-down to the lower power supply, in the usual CMOS fashion. Here, they are also cross coupled into an SRAM so that node N2 or node N4 may be high and the other low. Line
PX may select the SRAM through transistor T12 so that data may be written on line PY (where the data may be furnished by a processor). Output node N2 drives the gate of transistor T10, making it conductive when the gate is high or non-conductive when
the gate is driven (by programming the SRAM) to a low or off state. The transistor T10 is coupled between the Y conductive line and the X conductive line.
The programmable connection may be characterized by its worst case capacitance and resistance over the voltage and temperature range of the lines interconnected, a lower resistance when "on" providing less delay and better voltage margin. A
higher resistance when "off" provides lower leakage and battery drain, as well as improved voltage margin by reducing line and driver voltage drop from leakage.
In the SRAM type programmable connection example shown in FIG. 1, the source to drain "on" resistance is lower for voltages on the coupled X and Y lines coupled that are less than the power supply to which the gate is driven, since the resistance
from source to drain of the n-channel transistor tends to increase when the source or drain voltages approach the gate voltage. Accordingly, in some versions of greater complexity, the n-channel transistor T10 may have a special low threshold voltage Vt
or may be in parallel with a p-channel with gate driven by node N4. This full mux approach provides lower resistance but at the expense of greater capacitance and increased chip area for each matrix switch.
As a further example, to make such an approach non-volatile, the SRAM in FIG. 1 may be replaced by an EPROM, EEPROM, or Flash transistor properly loaded to drive the n-channel transistor T10, or the SRAM may be mirrored with non-volatile memory
such as FeRAM. Programming the non-volatile memory may be accomplished with a special higher voltage or current for the non-volatile element. However, such an approach increases process complexity.
Further, both the SRAM or the non-volatile alternative require considerable area in the base silicon to implement the switch, since the cross-point transistor alone may take up considerable area that could otherwise be dedicated to logic and
interconnect. Further, considerable extra interconnect is necessary to X-Y select the SRAM or its non-volatile equivalent, such as PX and PY wires at each intersection to uniquely select the SRAM cross-point transistor driver or non-volatile programming
element as shown in FIG. 1. Extra interconnect similarly may require extra chip area or interconnect layers that may raise cost and complexity of the delivered product.
The programmable connections in field programmable devices such as FPLAs may be formed as non-volatile anti-fuses at the X-Y interconnect. Products using anti-fuses (for example FPLAs from Actel, Inc.), desirably reduce the chip area and layers
dedicated to programming the programmable connection, by reducing the semiconductor active devices and interconnect (e.g. PX and PY) at each switch. This may also free up base silicon by putting the cross-point as a thin-film layer between interconnect
layers. FIG. 2 shows an anti-fuse 10 coupled between an X line X1 and a Y line Y1. The anti-fuse 10 acts as an OPEN connection before it is programmed. The anti-fuse may be implemented using an insulative breakdown material that is broken down to
provide a conductive pathway through application of a sufficiently high voltage across the material. The anti-fuse may be a metal-metal anti-fuse. Once programmed to a lower resistance state, an anti-fuse cannot be readily reversed. Accordingly,
testing in the field may be difficult and reversing a programmed anti-fuse may not be possible.
Manufacturers of equipment may find an error in FPLA operation after programming at the factory and shipment to the customer that could be fixed if the programming is reversible, perhaps allowing correction through remote dial-up and download to
re-program the logic if the cross-point programming is reversible. Or, the chip may be removed in the field and re-programmed by plugging into an adaptor to a computer.
However, while such an option is possible with SRAM or its non-volatile equivalent, such an option may not be possible with a fuse-based or anti-fuse based approach. Instead, the part may instead be removed and replaced at considerable expense
to the manufacturer and inconvenience to the customer.
Further, due to the testing limitations of using irreversible links, testing of the arrays intended for use by the customer may be done only indirectly by programming spare but representative anti-fuses on a fuse or anti-fuse based interconnect
approach before a part is shipped. However, actual programming of (untested) links used by the customer may be unsuccessful, since the links or cross-points actually used may be defective since they are untested before being shipped or used.
Programmable connections found unprogrammable may require return of the unit to the factory or even replacement in the final equipment if personalization is done after assembly.
Each of these discards may be at successively higher cost and require an undesirable manufacturing and field use flow which is incompatible with a more preferred zero-defect manufacturing and use. To better improve "yield" and reduce defects in
the field, the size and complexity of irreversible fuse or anti-fuse based approaches may be limited to relatively small arrays of interconnect compared to the more testable SRAM based approaches.
Further, the non-SRAM based approaches may add processing steps, beyond those of making the logic to be interconnected, that excessively raise cost. Customer preferences for lower cost suggest that such additional processing steps are preferably
offset by reduced chip size, processing steps, and reduced test cost relative to SRAM, since SRAM may take up more chip area but does not add extra process steps.
Accordingly, there is a need for a testable field programmable matrix array using a non-volatile programmable connection that is reversible in the field.
SUMMARY OF THE INVENTION
One aspect of the present invention is a programmable connection comprising a programmable resistance material such as a phase-change material. Such a thin-film programmable connection may be located and fabricated between the intersection of
the lines to be coupled by programming. Such a programmable connection may be programmed by the lines to be coupled, without additional programming lines located at or connected to the programmable connection. Instead, the programming control lines and
programming devices may be located anywhere along the interconnect lines, and, for example, more conveniently and efficiently on the ends of the interconnectable lines. Thus the programming devices and lines are shared across more than one programmable
connection to reduce programming overhead area for improved efficiency and cost.
The low resistance or set state of the phase-change material may be used where a CLOSED connection or short is desired between the layers of interconnect. The high resistance or reset state may be used where an OPEN connection is desired between
the layers. Leakage through OPEN connections may be reduced by lowering the power supply relative to the threshold voltage Vth of the phase change material, or by raising Vth relative to the normal operating range of the power supply.
To further reduce power on unused cross-points, the programmable connection may further comprise a thin-film breakdown layer. The breakdown layer is preferably formed of a dielectric material. The breakdown layer may be disposed such that it is
serially coupled with the phase-change material between the interconnected X and Y lines. In this case, the initial programming to a CLOSED connection entails not only setting the phase-change material to its low resistance state but also creating one
or more conductive pathways through the breakdown layer by puncturing or breaking it down with voltage or current.
The programmable connection, preferably formed at a cross-point, may be tested by programming the phase-change material to the high resistance reset state and then to the low resistance set state. It is noted, that only those phase-change
programmable connections which may potentially be CLOSED (initially or later) would need their breakdown layers penetrated at factory or at initial customer test. For example, if a customer knows that certain cross-points in a general purpose FPLA will
probably not be used in certain applications, the breakdown layers of the corresponding programmable connections need not be penetrated. Since the breakdown layer causes the programmable connection to have higher impedance until penetrated, the leakage
is thereby reduced while retaining general flexibility at each X-Y interconnection to program it later.
In sections of the design where lower resistance is desired at a cross-point, such as to drive the heavy capacitance load of a driver device input, several X-Y lines may be wired in parallel. Alternately, a small buffer gate may be permanently
wired-in to drive the higher capacitance input. Permanently wired interconnects may also be used for other logic connections in order to reduce the number of programmable connections, thereby further reducing leakage as well as test requirements.
Alternately, an SRAM programmable connection (or one or more other existing alternatives) may be wired in parallel with or used on the same chip with the phase-change programmable connections disclosed herein.
The breakdown layer may have an adequately high resistance so that no significant increase in leakage or battery drain occurs for those programmable connections having a breakdown layer that is not selected and penetrated.
Advantageously, the programmable connection may be made as a thin-film phase-change material and located between the interconnect conductive layers, preferably reducing chip size and/or freeing up more underlying chip area for logic while still
being reversible for improved testability and field repair/changes. The thin-film programmable connection may comprise a phase-change material as well as a breakdown layer separating the material from one of the conductive layers. The breakdown layer
is penetrated in those programmable connections which are actually programmed to a low resistance or tested to assure field programmability. With testability as described herein, a limitation against use of a thin-film programmable connection for larger
logic arrays is overcome.
To further assist testability, an optional read current source may be used that includes, for example, an operational amplifier and a reference voltage VREF (as an input to the operational amplifier) to read and confirm the resulting resistance
of a programmable connection after programming. (A re-write may be initiated if the results are not acceptable). Such reference voltage VREF may be adjusted to be a fixed value that is adjusted at probe to fit wafer characteristics, and may also be
dynamically adjustable to be higher when reading a phase-change programmable connection programmed to the high resistance or reset state, and VREF may be adjusted lower, by on-chip electronic means, when reading a programmable connection programmed to
the low resistance or set state (such adjustment to assure additional resistance margin beyond the resistance merely required).
Another aspect of the invention is an integrated circuit, comprising: a plurality of first conductive lines; a plurality of second conductive lines; and a plurality of programmable connections, each of the programmable connections coupled between
one of the first conductive lines and one of the second conductive lines, each of the programmable connections comprising a phase-change material, wherein there is no active device coupled in series with the phase-change material between its
corresponding first and second conductive lines. Active devices include transistors, diodes and threshold switches.
Another aspect of the invention is an integrated circuit, comprising: a plurality of first conductive lines; a plurality of second conductive lines; and a plurality of programmable connections programmably coupling the plurality of first
conductive lines to the plurality of second conductive lines, at least one of the programmable connections comprising a phase-change material, wherein there is no active device coupled between the phase-change material and the plurality of first
conductive lines or the plurality of second conductive lines.
Another aspect of the invention is an integrated circuit, comprising: a plurality of first conductive lines; a plurality of second conductive lines; and a plurality of programmable connections, each of the programmable connections programmably
coupling a corresponding one of the first conductive lines to a corresponding one of the second conductive lines, at least a certain one of the programmable connections comprises a phase-change material, wherein there is no active device coupled between
the phase-change material and its corresponding first or second conductive lines.
Another aspect of the invention is an electronic system, comprising: a first conductive line; a second conductive line; and a programmable connection coupled between the first conductive line and the second conductive line, the programmable
connection comprising a phase-change material, wherein there is no active device in series with the phase-change material between the first and second conductive lines.
Another aspect of the invention is a programmable matrix array, comprising: a programmable element coupled between a row line and a column line, the programmable element comprising a phase-change material, wherein there is no active device
coupled in series with the phase-change material between the row line and the column line.
Another aspect of the invention is a method of coupling a first conductive line to second conductive line, comprising: providing a phase-change material coupled between the first and second conductive lines, wherein there is no active device in
series with the phase-change material between the first and second conductive lines; and programming the phase-change material between a first resistance state and a second resistance state. In one embodiment, at least one of the resistance states may
be a state other than the reset state. Preferably, one of the states is the set state.
Another aspect of the invention is an integrated circuit, comprising: a plurality of first conductive lines oriented in a first direction; a plurality of second conductive lines oriented in a second direction different from the first direction;
and a programmable element comprising a first electrode, a second electrode and a phase-change material, the first and second electrodes for supplying an electrical signal to the phase-change material, the first electrode directed connected to one of the
first conductive lines, the second electrode directed connected to one of the second conductive lines.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows an example of a volatile programmable connection using SRAM technology;
FIG. 2 shows a programmable connection using anti-fuse technology;
FIG. 3A is an embodiment of a programmable matrix array of the present invention using programmable connections comprising a phase-change material;
FIG. 3B is an embodiment of a programmable matrix array of the present invention using different types of programmable connections;
FIG. 4A shows an embodiment of a programmable connection of the present invention comprising a phase-change material;
FIG. 4B shows an embodiment of a programmable connection of the present invention comprising a phase-change material and electrodes;
FIG. 5A shows an embodiment of a programmable connection of the present invention comprising a phase-change material and a breakdown layer;
FIG. 5B shows an embodiment of a programmable connection of the present invention comprising a phase-change material and a breakdown layer;
FIG. 5C shows an embodiment of a programmable connection of the present invention comprising a phase-change material, a breakdown layer and electrodes;
FIG. 5D shows an embodiment of a programmable connection of the present invention comprising a phase-change material, a breakdown layer and electrodes;
FIG. 5E shows an embodiment of a programmable connection of the present invention comprising a phase-change material, a breakdown layer and electrodes;
FIG. 5F shows an embodiment of a programmable connection of the present invention comprising a phase-change material, a breakdown layer and electrodes;
FIG. 6A is a current-voltage curve for a programmable connection comprising a phase-change material;
FIG. 6B is a current-voltage curve for a programmable connection comprising a phase-change material;
FIG. 6C is a current-voltage curve for a programmable connection comprising a phase-change material and a breakdown material;
FIG. 6D is a current-voltage curve for a programmable connection comprising a phase-change material and a breakdown material;
FIG. 7 is a current-resistance curve for a volume of phase-change material;
FIG. 8 is an example of a block diagram of a programmable logic array;
FIG. 9 is an implementation of the block diagram of FIG. 8 using programmable connections comprising a phase-change material;
FIG. 10 is an embodiment of a programmable logic device using programmable connections comprising a phase-change material;
FIG. 11A shows a symbol for a programmable connection that comprises a phase-change material;
FIG. 11B shows a symbol for a programmable connection that includes a phase-change material but does not include a breakdown layer;
FIG. 11C shows a symbol for a programmable connection that includes a phase-change material and a breakdown layer wherein the breakdown layer has not been broken down;
FIG. 11D shows a symbol for a programmable connection that includes a phase-change material and a breakdown layer wherein the breakdown layer has been broken down;
FIG. 11E shows a symbol for a direct connect or hard wired connection;
FIG. 11F shows a symbol for a programmable connection that is based on SRAM technology;
FIG. 11G shows a symbol for a programmable connection based on anti-fuse technology;
FIG. 12 shows a block diagram of an electronic device comprising memory, a controller, a wireless interface, a camera, SRAM, I/O and a battery;
FIG. 13A shows how a diode may be used as an isolation device with a phase-change memory element;
FIG. 13B shows how a transistor may be used as an isolation device with a phase-change memory element; and
FIG. 13C shows how a transistor may be used as an isolation device with a phase-change memory element.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3A shows an embodiment of an electrically programmable matrix array 100 of the present invention. The matrix array includes a first set of conductive lines X1 through X4 which are also referred to as X lines. The matrix array includes a
second set of conductive lines Y1 through Y4 which are also referred to as Y lines. In the example shown there are four X lines and four Y lines. However, more generally, there may be one or more X lines, and there may be one or more Y lines.
Preferably, there are a plurality of X lines. Preferably, there are a plurality of Y lines.
Each of the X lines preferably crosses (either over or under) each of the Y line at an angle. The angle may be substantially 90.degree. (that is, substantially perpendicular). The points at which they cross over are referred to as the
cross-over points or cross-points.
The embodiment of the matrix array 100 includes a plurality of programmable connections CPS. Each programmable connection CPS is coupled between an X line and a Y line. In the embodiment shown, it is seen how each programmable connection CPS is
electrically coupled between a corresponding one of the X lines and a corresponding one of the Y lines. Furthermore, in the embodiment shown, it is seen that the each programmable connection CPS is electrically coupled to one of the X lines and one of
the Y lines.
While, a programmable connection is coupled between a corresponding one of the X lines and a corresponding one of the Y lines, the programmable connection does not have to be physically disposed between the two corresponding lines. It may, for
example, be electrically coupled to each of the lines without being physically located between the lines.
In the embodiment shown, each programmable connection CPS comprises a phase-change material. Generally, any phase-change material which is programmable between at least a first and second resistance state may be used. Preferably, the
phase-change material may comprise at least one chalcogen element. An example of a phase-change material that may be used is Ge.sub.2Sb.sub.2Te.sub.5. This alloy is also referred to as GST 225. GST 225 may be preferred since targets are readily
available commercially and may be deposited by standard semiconductor equipment.
Other examples of phase-change materials which may be used are discussed in U.S. Pat. Nos. 5,166,758, 5,296,716, 5,341,328, 5,359,205, 5,406,509, 5,414,271, 5,534,711, 5,534,712, 5,536,947, 5,596,522, 5,825,046 and 6,087,674, all of which are
hereby incorporated by reference herein.
As used herein, a programmable connection that includes a phase-change material may also be referred to as a phase-change programmable connection.
It is noted that other embodiments of the invention are possible where a programmable connection is formed from programmable resistance materials that can be electrically programmed between at least a first resistance state and a second
resistance state, but which are not phase-change materials. Hence, it is possible that the programmable connection be made from programmable resistance materials other than phase-change materials.
The programmable connection CPS comprises a phase-change material. FIG. 4A shows a simplified diagram of an embodiment of a programmable connection CPS that consists essentially of a phase-change material 200. The phase-change material is
electrically coupled between an X conductive line X1 and a Y conductive line Y1.
In the embodiment of FIG. 4A, the phase-change material is electrically coupled to both the X1 line and Y1 line. In the embodiment of FIG. 4A, the phase-change material is disposed between the X1 line and Y1 line. However, the phase-change
material does not have to be physically disposed between the X1 line and the Y1 line. In this embodiment, the phase-change material is directly connected to both the X1 line and the Y1 line.
FIG. 4B shows a simplified diagram of another embodiment of a programmable connection CPS comprising a phase-change material electrically coupled between an X line X1 and a Y line Y1. In the embodiment shown in FIG. 4B, the phase-change material
200 is electrically coupled between the X1 line and Y1 line. In this embodiment, the phase-change material is coupled to the X1 line and to the Y1 line but is not directly connected to either. This embodiment further includes a first electrode (or
contact layer) 210A electrically coupled between the phase-change material 200 and the X conductive line X1, and a second electrode 210B (or contact layer) electrically coupled between the phase-change material 200 and the Y conductive line Y1. In the
embodiment shown in FIG. 4B, the phase-change material 200 is coupled to the X1 line through the electrode 210A. Likewise, the phase-change material is coupled to the Y1 line through the electrode 210B. In this particular embodiment, the first
electrode 210A is directly connected to the X1 line while the second electrode 210B is directly connected to the Y1 line. (Other embodiments are possible where the electrodes are not directly connected to the X and Y lines).
In FIG. 4B, each of the electrodes 210A and 210B is shown as a single layer. However, each electrode may be formed as a plurality of layers. Also, each layer may have multiple sublayers. In addition, while two electrodes 210A and 210B are
shown, it is possible that only a single electrode (either 210A or 210B) be used. In the embodiments shown in FIGS. 4A and 4B, the programmable connection CPS is electrically coupled to both the X conductive line and the Y conductive line.
Generally, the electrodes 210A and 210B may be formed of a conductive material. Examples of conductive materials which may be used include, but are not limited to, n-type doped polysilicon, p-type doped polysilicon, p-type doped silicon carbon
alloys and/or compounds, titanium-tungsten, tungsten, tungsten silicide, molybdenum, titanium nitride, titanium carbon-nitride, titanium aluminum-nitride, titanium silicon-nitride, and carbon.
In the embodiment shown in FIGS. 4A and 4B the conductive lines X1 and Y1 preferably cross each other (in the embodiment shown, Y1 crosses over X1). Line Y1 is preferably oriented in a first direction while line X1 is preferably oriented in a
second direction which is different from the first direction. Line Y1 and line X1 may be substantially perpendicular to each other.
In another embodiment of the invention, the phase-change programmable connection CPS may further include one or more breakdown layers. The breakdown layer is preferably a layer of a dielectric material. The breakdown layer is preferably
electrically coupled between the phase-change material and one of the conductive lines X1 or Y1. An addition breakdown layer may be electrically coupled between the phase-change material and the other conductive line.
Embodiments of the invention shown in FIGS. 5A through 5F include a phase-change material 200 and a breakdown layer 300. In the embodiments shown in FIGS. 5A though 5F, the programmable connection CPS is electrically coupled between the X1 line
and the Y1 line. In the embodiments shown in FIGS. 5A through 5F, the programmable connection CPS is electrically coupled to both the X conductive line X1 and the Y conductive line Y1. In the embodiments shown in FIGS. 5A through 5F, the programmable
connection CPS is shown as being physically disposed between the X and Y lines. However, in other embodiments, this does not have to be the case.
FIGS. 5A and 5B show a programmable connection CPS (without electrodes) coupled between an X conductive line and a Y conductive line. In FIG. 5A, the breakdown layer is electrically coupled between the X line X1 and the phase-change material
200. In FIG. 5B, the breakdown layer 300 is electrically coupled between the phase-change material 200 and the Y line Y1.
In the embodiments shown in FIGS. 5A and 5B, the phase-change material and the breakdown material are in electrical series with respect to the current path between the X1 line and the Y1 line. Hence, if the breakdown material is not broken down,
the electrical resistance through the programmable connection CPS is high. If a voltage is applied across the X1 line and Y1 line, there is substantially no current flow between the X1 line and the Y1 line through the programmable connection CPS
regardless of the state of the phase-change | | |
